In the development of integrated circuits such as an SRAM memory circuit with internal operations synchronized with an internally or externally generated input signal such as a clock signal or other input signal that is nonperiodic, it is often necessary to set a signal line such as a WLEN (“word line enable”) or BLEN (“bit line enable”) signal line to a logic high state for a short period of time to enable the internal operation. Generally, after the short period of time, the signal line state is returned to a logic low state to terminate the operation by a signal such as an internally or externally generated clear signal (“CLEAR”). It is essential when enabling internal operations of a device that the signal on the signal line be sufficiently long to assure its normal signaling function, but not unnecessarily long so as to slow overall device operation. Device speed, such as a memory cycle time, is often a carefully watched performance metric for product market acceptance. Device speed receives substantial attention during a product development phase. Thus, it is important to generate a signal on such a signal line with minimum acceptable pulse duration.
A signal line, such as a WLEN or BLEN signal line, is often coupled to an extensive set of circuit nodes, each with capacitance that may be unknown or substantially variable across manufacturing runs for a product. In addition, such signal lines are generally maintained in a logic high or logic low state by a latch such as a latch formed with a pair of cross-coupled inverters, where the output of one inverter is coupled to the input of the other. Latches formed with such inverters require significant drive energy to be transitioned from one logic state to the other. Therefore, the minimum drive signal magnitude and its duration to transition the state of a latch and associated circuit nodes can also be substantially variable across manufacturing runs, and even be substantially variable over a range of device operating temperatures. A need thus exists for an improved process and method to produce a signal on a signal line in response to an edge transition of an input signal that can overcome such deficiency.